The present invention relates in general to communication circuits, and is particularly directed to a ringing voltage power management circuit. The ringing voltage power management circuit is configured to extract an isolated high-value intermediate voltage from a central office powered digital subscriber line through a current limiting circuit, and to charge a storage capacitor that serves as an energy reservoir for the ring generator of a subscriber line circuit. The storage capacitor and the current limiting circuit isolate the peak power drawn by the ringing load from the telephone line and translate the ringing signal""s 20 Hz ripple to the sub-Hz oscillations of the ringing cadence (ring on/off cycle).
Digital subscriber line (DSL) services are frequently used to deliver POTS (plain old telephone service) and digital data over a single pair of telephone wires. A common implementation is for DSL terminals to be installed in the central office and near the customer site (remote terminal), with power for the remote terminal (RT) being supplied over the DSL line pair from the central office terminal (COT). Because the POTS ringing voltage is not delivered over the DSL line, the ringing voltage must be generated at the remote terminal, which creates two problems.
First, the peak power demand of the ringing voltage can limit the deployment range of the RT, as the resistance of the telephone line limits the amount of power that can be delivered to the RT for a fixed COT line voltage. The more power drawn by the RT, the shorter the maximum possible line length for its deployment. The only options to increase deployment range are to increase the COT line voltage or reduce the peak power demands of the RT. Safety considerations and standards mandate limiting COT line voltages, so that power management in the form of peak power limiting of the RT is essential.
The second problem is the fact that noise associated with the generation of the ringing voltage can mix with the DSL signal, causing significant performance problems of the digital circuits. Some DSL systems are very sensitive to ringing voltage ripple, because the 20 Hz ring frequency is high enough to interfere with the signal, yet too low for the analog or digital filters of the signal path to attenuate. Passive power filtering between the RT input and the ringing generator requires a relatively physically large circuit and may not be practical, because of the low frequency and the amount of attenuation required. For a 50 Vrms ringing voltage, 80-100 dB of attenuation may be required at 20 Hz.
In accordance with the present invention, both of these problems are effectively solved in a cost and space-efficient manner, by a ringing voltage power management circuit, that is configured to generate an isolated high-value voltage from the line power through a current limiting circuit, and use this isolated high-valued voltage to charge a storage capacitor that serves as an energy reservoir for the ringing voltage generator. The storage capacitor and the current limiting circuit isolate the peak power drawn by the ringing load from the telephone line RT input and translate the 20 Hz ripple to the sub-Hz oscillations of the ringing cadence (ring on/off cycle).
Pursuant to a preferred embodiment of the invention, respective currents flowing in secondary transformer windings of a main DC-DC converter are rectified and smoothed by diode-capacitor pairs to provide a relatively high isolation voltage (e.g., 200 VDC) for charging the storage capacitor, and a bias voltage for a pulse width modulator of a buck pre-regulator. The relative large magnitude isolation voltage is coupled to the storage capacitor through a current limiting circuit. The buck pre-regulator converts the voltage across the storage capacitor into a DC ringing rail voltage coupled to a voltage input port of the SLIC, which generates the ringing voltage. The pre-regulator contains a pulse width modulator (PWM) control circuit, that is switched on and off at a frequency considerably higher than the ring frequency. The PWM control circuit is coupled to the gate of a MOSFET switch, which has its drain-source path coupled with the storage capacitor and an output LC filter.
In response to the MOSFET switch being gated on by the modulation waveform generated by the PWM control circuit, current flows out of the storage capacitor through the MOSFET and the LC filter into the SLIC and returns via the ringing voltage rail. When the MOSFET is switched off, the ringing rail voltage is supplied by the discharging of the output LC filter. The output voltage is regulated by the duty cycle of the PWM modulation of the MOSFET. The ringing rail voltage (the buck pre-regulator output) is equal to the voltage across storage capacitor multiplied by the duty cycle of the PWM waveform.
When the ringing voltage control signal disables the ringing output of the SLIC, there is no load on the current limiting circuit, and the storage capacitor is charged up to approximately the high valued isolation voltage. When ringing is enabled, current is supplied to the buck pre-regulator from the current limit circuit and the storage capacitor. Additional current is drawn from the storage capacitor by the buck pre-regulator. As the storage capacitor discharges, its output is monitored via a feedback control path from a voltage divider, and the buck pre-regulator control circuit increases the duty cycle D of its PWM output waveform, so as to maintain a constant ringing voltage to the SLIC. During the six second ring interval, the current delivered by the isolation voltage never exceeds the value set by the current limit circuit, so that the power delivered over duration of the ringing period is constant.